The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Substrate processing systems may be used to perform deposition of film on a substrate. Substrate processing systems typically include a processing chamber defining a reaction volume. A substrate support such as a pedestal, a chuck, a plate, etc. is arranged in the processing chamber. A substrate such as a semiconductor wafer may be arranged on the substrate support. During atomic layer deposition (ALD), one or more ALD cycles are performed to deposit film on the substrate. For plasma-based ALD, each ALD cycle includes precursor dose, purge, RF plasma dose, and purge steps.
During deposition of film onto the substrate, deposition may also occur in locations other than the top portion of the substrate where it is desired. Deposition may occur along a backside edge of the substrate (hereinafter “backside edge deposition”). The backside edge deposition may cause problems during subsequent processing. In spacer applications, backside edge deposition may cause defocusing issues during subsequent lithography steps.
Since ALD films are inherently conformal (due to the surface-saturated mechanism), both half reactions should be minimized on the backside of the substrate. In other words, flow of precursor to the backside of the substrate during the precursor dose should be minimized or eliminated. In addition, plasma wrap around to the backside of the substrate also needs to be minimized or eliminated.
Typically, purge gas such as argon may be directed at the backside edge of the substrate. However even when using the purge gas, backside deposition may still occur. In some examples, greater than 250 A of backside deposition at 3 mm from the wafer edge may occur.